I received an interesting demonstration of Icinergy's SOCarchitect tool via a WebEx session last week. The SOCarchitect tool assists with physical design planning and provides designers with a visual environment to capture the architectural and physical design requirements of complex System-On-Chip designs.

If you've never used WebEx for interactive meetings and demonstrations, it is a real time saver and you should check it out. I couldn't travel for a demonstration last week, as I had several meetings in Portland; so I met with representatives from Icinergy Software Company to receive a demonstration of their SOCarchitect tool "on the web". Their applications engineer Yves Gagnon, was located in Ottawa, Canada and their sales engineer Carol Hallett, was located in San Jose, California while I was in my office in Portland, Oregon.

First, Carol presented a company background presentation on Icinergy Software Company from San Jose, followed by a live demonstration of the SOCarchitect tool by Yves from Ottawa. This was a very effective way to give a remote demonstration, as Yves was able to demonstate capabilities of the tool interactively in response to my questions.

Since I was using a web browser on my laptop to view the demonstration, I thought it might be fun to run PaintShop Pro as the demonstration was being given, in order to do some screen captures. I assigned a function key on the keyboard to perform screen captures, and after a little fiddling around was able to get some reasonable images. Now I could provide some feedback to my hosts, as to what the demonstration looked like at my end. If you want to see the full resolution images, just click on one of the "thumbnail" views below and the full resolution image will load into a separate browser window.

The SOCarchitect tool is used primarily at the architectural and HDL levels of the design process, and provides a hierarchical system that allows the designer to visualize the floorplan and layout of the design. At the beginning of the design process there is often little to no detailed information about some sections of a complex SOC, because they have not been implemented yet. There may be very detailed information about other sections, such as compiled memories, embedded processors, or licensed IP blocks. SOCarchitect allows designers to enter the information at hand, and perform planning and estimation based on the target technology for the design. Blocks can be created dynamically, or can be instantiated using standard interfaces such as LEF and GDSII. They can be resized, moved, rearranged, or duplicated with immediate feedback on the effect the floorplan has on wiring congestion and delays. I particularly liked the hierarchical nature of the tool, which allowed you to push into a heirarchy and make changes at any level.

The hour-long demonstration was just enough to pique my interest in the tool, and I hope to be able to do a more detailed evaluation in a few weeks. Overall, this looked like just the kind of tool to kick off a new design project, particularly one that requires collaboration between several team members and outside vendors. It looks to provide a nice coordinating view of a design as it evolves, and the PDF Data Sheet generation feature could be quite useful for documentation purposes.

	A basic outline floorplan view with wiring turned off.
	A floorplan view with rat's nest/interconnect wiring turned on. The red nets indicate timing violations based on block to block timing budgets.
	Using the Power Estimation Property Sheet to estimate device power consumption.
	Multiple views allow the designer to see connectivity, timing violations, routing density, and other views against one another for comparison.
	A really nice feature of SOCarchitect is the ability to create a PDF Data Sheet for the design that includes the floorplan and detailed design parameters.
	An example of a vendor plug-in to generate custom memory blocks.

SOCarchitect™ is a registered trademark of Icinergy Software Company