Assorted EDA References

• UCLA Metrics
• Intel Nike Data Model
• scripteda By Pinhong Chen
• EDA - EDP Program
• gsrc990919summary
• Intel ASICS
• Design Flow Slides
• ASSET Tools
• Behavioral and Physical Synthesis
• Synthesis by Sudha
• Behavioral Synthesis Integratrion
• Intel ASICS
• ARM IP Development
• unified synthesis presentation
• unified synthesis
• Synopsys Primetime SI
• IBM ASICS
• Synopsys Euro
• Cadwire
• Design Flow By R.Davis
• (UML Flow)
• (UML diagramming)
• Video Compression
• Get2Chip Topomo
• Behavioral Synthesis Report
• Deep Sub Micron
• Linux EDA
• EDP01 Program
• Numerical Methods in Markov Chain Modelling (1992)
• Fast Integration of EDA Tools and Scripting Languages
• Collect Slides
• Design Planning Methodology for Rapid Chip Deployment
• EDA Spine
• Methodology Searches
• ISS Design Flows
• Rita GLover EDA overview
• Logic Synthesis Methodology
• Magma Preso
• Bleeding Edge
• RASSP Methodology
• Adv. Micro Methodology
• Hardware/Software Iteg. Method
• HDL Focus
• SOC design
• Verifying Virtual Components And VC-Based SoC Designs
• VHDL _> SystemC
• Cadence Perforce Integration
• SourceForge EDA projects
• Writing Testbenches
• Rajesh Verilog Center
• Toshiba TDF Methodology
• LSI Logic Flexstream
• Silicon Arts
• Core Development
• UT Cadence Help
• Desktop Engineering Site
• Zuken-Redac Standards
• European Chips & Systems Inst.
• Programmage FPGA Platform
• DA Index
• ASIC/SOC
• condesinc
• Encapsulate Thesis Introduction
• Cadence VCC Backgrounde
• VSI Overview
• EDA Terms Dictionary