http://www.moxon.com Moxon Design - Topics in Integrated Circuit and Product Design en-us Moxon Design is Copyright 1991-2001, Tom Moxon 2002-07-28 Moxon Design Tom Moxon integrated circuit design asic soc eda semiconductors http://www.moxon.com/2001/11/1/img/md88x31.gif http://www.moxon.com/ 88 31 a guide for the design of the next generation of electronic products http://www.eedesign.com/features/exclusive/OEG20020725S0054 EEDesign Exclusive - In this final installment of his 5-part series, ASIC designer Tom Moxon shows how you can pull IC design flows together using resource management, dependency graphing tools and the Resource Definition Framework (RDF). Tom Moxon asic soc eda 2002-07-25 articles 0 http://www.eedesign.com/features/exclusive/OEG20020628S0107 EEDesign Exclusive - In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical optimization and layout design flows, and will discuss signal integrity issues and show how they are currently being addressed. Tom Moxon asic soc eda 2002-06-28 articles 0 http://www.eedesign.com/features/exclusive/OEG20020307S0039 EEDesign Exclusive - In Part 2 of this series,consultant and ASIC designer Tom Moxon covered several trends in virtual silicon prototying design flows. In this installment of the series he'll show how to link these flows with several different RTL synthesis design flows. Tom Moxon asic soc eda 2002-03-07 articles 0 http://www.eedesign.com/features/exclusive/OEG20020115S0034 EEDesign Exclusive - In Part I of this series,consultant and ASIC designer Tom Moxon outlined some of the challenges faced in deep submicron ASIC design and discussed the current trends in Virtual Silicon Prototying design flows. In this installment of the series, he'll demonstrate several detailed design flows used with pre-RTL and RTL exploration tools from Icinergy Software, Tera Systems, and InTime Software. Tom Moxon asic soc eda 2002-01-15 articles 0 http://www.eedesign.com/story/OEG20011218S0058 EEDesign Exclusive - Consultant and ASIC designer Tom Moxon has evaluated deep submicron IC design flows using open-source cores and new EDA tools. He will report his findings in a five-part article series for EEdesign. In this initial article, Moxon provides an overview of the emerging deep submicron design flow. Subsequent articles will provide more details about tools from vendors such as InTime, Incentia, Icinergy, and Tera Systems. Tom Moxon asic soc eda 2002-01-14 articles 0 http://chipvault.sourceforge.net/ Kevin Hubbard has released ChipVault a lightweight design management tool for large chip design projects. The ChipVault design organizer provides hierarchical HDL source file organization, hierarchical viewing, block instantiation, revision and issue tracking, and hooks for launching EDA tools from the framework. Written in Perl, the tool is small and efficient. Kevin is currently working on a Tk GUI port of the tool, and is requesting Alpha testers for the graphical version. Tom Moxon asic soc eda 2001-12-17 articles 0 http://snverilog.sourceforge.net/ Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many verilog files. It parses verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling. Source Navigator was developed by Cygnus Software as an IDE (Integrated Development Environment) for software engineers and was later released under the GPL by Red Hat. Source Navigator supports many languages including C, C++, Tcl, Java, Fortran, and COBOL. Tom Moxon asic soc eda 2002-01-24 articles 0 http://www.moxon.com/2001/12/04/channels/eda/200112041500.html I received an interesting demonstration of Icinergy's SOC Architect tool via a WebEx session last week. The SOCarchitect tool assists with physical design planning and provides designers with a visual environment to capture the architectural and physical design requirements of complex System-On-Chip designs. Tom Moxon asic soc eda 2001-12-04 articles 0 http://www.moxon.com/2001/11/16/channels/xml/200111161130.html A number of people have have asked me, "Okay, so what does a netlist in XML look like anyway?". I've converted a small circuit example for people to examine using the E-Studio tool from Electronic Tools Company and have made it available for discussion purposes. Tom Moxon asic edaxml Integrated Circuit Design 2001-11-16 articles 0 http://www.moxon.com/channels/synthesis/200111101130.html There has been a thread about the generation of statistical wireload models in ESNUG 377 and 378 lately, with several good references quoted there. However I have some cautions about depending too heavily on Statistical Wireload Models. Tom Moxon asic wireload models synthesis 2001-11-10 articles 0 http://www.moxon.com/1997/1/1/supercon/ Concurrent engineering strategies and ASIC design methodologies used to develop several large-scale, submicron ASIC products; implemented using multivendor EDA tools running on a heterogeneous network of multiprocessor servers. Tom Moxon asic design 2001-11-09 articles 0 http://www.moxon.com/2001/11/1/resources/edatools/ A bookmarks format index of EDA Software websites.